Testbench For Entitiy with package - VHDL -

i have problems in creating testbench test module used package. package contains block of array accessed in different process.

-------------------- package --------------------- library ieee; use ieee.std_logic_1164.all; package my_array_pkg  type my_array array ( 0 9) of std_logic_vector(3 downto 0);  end my_array_pkg; 

and top entity.

----------------- top entity -------------------------     library ieee;     use ieee.std_logic_1164.all;     use work.my_array_pkg.all;     use ieee.numeric_std.all;  entity pkt_top port ( sys_clk  : in std_logic;         reset : in std_logic;         an_en   : out std_logic_vector(3 downto 0);         seg_cathodes    : out std_logic_vector(6 downto 0) );       end pkt_top;  architecture behavioral of pkt_top  signal clk1hz, clk256hz : std_logic; signal my_digit : my_array;  component clock_1hz     port ( sys_clk  : in  std_logic;                 reset       : in std_logic;                 c_256hz : out std_logic;                 c_1hz       : out std_logic                 ); end component;  component array_count port ( c_1hz    : in std_logic;         reset   : in std_logic;         digit   : out my_array         ); end component;  component display_driver port ( reset            : in std_logic;         c256hz          : in std_logic;         c_1hz           : in std_logic;         digit_in        : in my_array;         seg_cathodes    : out std_logic_vector(6 downto 0);         an_en           : out std_logic_vector(3 downto 0)     ); end component;  begin  c1 : clock_1hz -- gives 2 clock divisions.     port map ( sys_clk, reset,clk256hz,  clk1hz);  c2 : array_count -- initialize array numbers on every 1hz edge     port map ( clk1hz, reset, my_digit);  c3 : display_driver -- dispaly numbers on 7 segments 256hz switching time between segments.     port map (reset , clk256hz, clk1hz, my_digit, seg_cathodes, an_en);  end behavioral; 

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the code synthesizable , works on basys2 board, cannot simulate via testbench.

--------------------my testbench ------------------------- library ieee; use ieee.std_logic_1164.all; use work.my_array_pkg.all;  entity pkg_tb end pkg_tb;  architecture behavior of pkg_tb       -- component declaration unit under test (uut)      component pkt_top     port(          sys_clk : in  std_logic;          reset : in  std_logic;          an_en : out  std_logic_vector(3 downto 0);          array_test : inout  my_array;          seg_cathodes : out  std_logic_vector(6 downto 0)         );     end component;      --inputs    signal sys_clk : std_logic := '0';    signal reset : std_logic := '0';     signal my_digit : my_array;      --outputs    signal an_en : std_logic_vector(3 downto 0);    signal seg_cathodes : std_logic_vector(6 downto 0);     -- clock period definitions    constant sys_clk_period : time := 20 ns;  begin      -- instantiate unit under test (uut)    uut: pkt_top port map (           sys_clk => sys_clk,           reset => reset,           an_en => an_en,           array_test => my_digit,           seg_cathodes => seg_cathodes         );     -- clock process definitions    sys_clk_process :process    begin         sys_clk <= '0';         wait sys_clk_period/2;         sys_clk <= '1';         wait sys_clk_period/2;    end process;      -- stimulus process    stim_proc: process    begin               -- hold reset state 100 ns.         reset <= '1';       wait 100 ns;         reset <= '0';        -- insert stimulus here         wait;    end process;  end; --------------------------------------------------------------- 

when simulate isim gives error 'array_test' not being availabe in top entity, , if removed simulation remains blank.

any testbench please.

i can't see port named "array_test"in description of entity pkt_top. must declare an output port in pkt_top.